2 February 2026
Sr. Staff Engineer, RF Design
We’re looking for a hands-on Sr. Staff RF Design engineer to own the architecture, RTL implementation, and verification of digital logic for cellular transceiver RFICs. This role works closely with system, analog, and test engineers to translate requirements into reliable designs, develop verification environments, and support FPGA and silicon bring-up, debug, and characterization. The ideal candidate is technically independent, strong in RTL and verification, and comfortable driving issues to root cause across design and test.
Responsibilities
- Work with system engineers and analog designers to clarify control requirements for analog blocks and specifications for on-chip digital signal path blocks.
- Design and implement digital logic that meets those requirements and specifications;
- Develop and execute test plans for pre-synthesis verification. For high-speed serial interface, work with relevant designers to clarify requirements on FPGA code in lab test environment;
- Develop and verify that code. Support designers and test engineers in bring-up, optimization, and characterization phases of lab test and ATE test activity.
- Working with system engineers and analog designers, take primary responsibility for defining architecture, functionality, and timing requirements for digital part of cellular transceiver RFICs.
- With minimal technical guidance, develop RTL (register transfer language) code for control of analog circuitry and implementation of digital front-end signal paths and high-speed digital interfaces.
- In design phase, take primary responsibility for developing test benches for simulation and debug of RTL code, both stand-alone and in combination with digital models of analog blocks for top-level functional verification.
- Generate and present documentation for design reviews and write design reports.
- In preparation for test phase, with minimal technical guidance, develop, simulate, and verify FPGA code, execute workflow for programming FPGA, and perform stand-alone lab testing of FPGA platform.
- In test phase, participate in functional testing of transceiver RFICs and provide technical guidance to system engineers, analog designers, and test engineers to support performance testing. When issues associated with digital part of design are identified in test phase, proactively participate in investigation and verification of root causes, and in development and verification of solutions.
- Generate and present documentation for test reviews and write test reports for digital functionality.
Experience
Masters degree in Electrical Engineering, or a related field. Must have had coursework that laid foundation for:
- Familiarity with RTL design with Verilog/System Verilog
- Familiarity with middle-end design, including constraint specification, STA, formal equivalency, synthesis, and ATPG
- Familiarity with low-power design and DFT techniques
- Familiarity with lab equipment and techniques